Reuse Techniques for VLSI DesignRalf Seepold, Arno Kunzmann Springer Science & Business Media, 6. pro 2012. - Broj stranica: 153 Reuse Techniques for VLSI Design is a reflection on the current state of the art in design reuse for microelectronic systems. To that end, it is the first book to garner the input of leading experts from both research and application areas. These experts document herein not only their more mature approaches, but also their latest research results. Firstly, it sets out the background and support from international organisations that enforce System-on-a-Chip (SoC) design by reuse- oriented methodologies. This overview is followed by a number of technical presentations covering different requirements of the reuse domain. These are presented from different points of view, i.e., IP provider, IP user, designer, isolated reuse, intra-company or inter-company reuse. More general systems or case studies, e.g., metrics, are followed by comprehensive reuse systems, e.g., reuse management systems partly including business models. Since design reuse must not be restricted to digital components, mixed- signal and analog reuse approaches are also presented. In parallel to the digital domain, this area covers research in reuse database design. Design verification and legal aspects are two important topics that are closely related to the realization of design reuse. These hot topics are covered by presentations that finalize the survey of outstanding research, development and application of design reuse for SoC design. Reuse Techniques for VLSI Design is an invaluable reference for researchers and engineers involved in VLSI/ASIC design. |
Sadržaj
| 4 | |
2 | 10 |
2 | 16 |
CORPORATE DESIGN REUSE STRATEGY | 37 |
4 | 43 |
2 | 50 |
5 | 56 |
HARD IP REUSE METHODOLOGY FOR EMBEDDED | 63 |
3 | 81 |
ASPECTS OF REUSE IN THE DESIGN OF MIXED | 91 |
DESIGN REUSE EXPERIMENT FOR ANALOG | 103 |
REDESIGN OF AN MPEG2HDTV VIDEO DECODER | 111 |
REUSE CONCEPTS IN GROPIUS 125 | 124 |
LEGAL ASPECTS OF REUSE OF INTELLECTUAL | 139 |
80 | 148 |
INDEX | 151 |
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algorithmic analog application architecture attributes automation basic behaviour boolean business model cells chip circuit descriptions clock complex Computer concept core coversheet database system defined described design flow design for reuse design methodology design reuse DesignObject dfg-terms documentation ECSI effort environment European example Figure functionality GDSII Germany Gropius Gropius-3 hardware description language HDTV HiPEG IDCT implementation input instantiated integration Intellectual Property interface internal IP block k-processes Karlsruhe levels of abstraction library element MEDEA mixed signal systems module netlist node operational amplifiers output p-terms parameters polymorphic reusable component reuse library reuse technique reuser Robert Bosch GmbH scripts Semiconductor Shaper simulation specification standard static timing analysis structure synthesis system level systems-on-a-chip taxonomy template testbench tion traffic shaping types University of Karlsruhe verification Verilog VHDL video decoder virtual components VSIA