Reuse Techniques for VLSI DesignRalf Seepold, Arno Kunzmann Springer Science & Business Media, 31. ožu 1999. - Broj stranica: 153 Reuse Techniques for VLSI Design is a reflection on the current state of the art in design reuse for microelectronic systems. To that end, it is the first book to garner the input of leading experts from both research and application areas. These experts document herein not only their more mature approaches, but also their latest research results. Firstly, it sets out the background and support from international organisations that enforce System-on-a-Chip (SoC) design by reuse- oriented methodologies. This overview is followed by a number of technical presentations covering different requirements of the reuse domain. These are presented from different points of view, i.e., IP provider, IP user, designer, isolated reuse, intra-company or inter-company reuse. More general systems or case studies, e.g., metrics, are followed by comprehensive reuse systems, e.g., reuse management systems partly including business models. Since design reuse must not be restricted to digital components, mixed- signal and analog reuse approaches are also presented. In parallel to the digital domain, this area covers research in reuse database design. Design verification and legal aspects are two important topics that are closely related to the realization of design reuse. These hot topics are covered by presentations that finalize the survey of outstanding research, development and application of design reuse for SoC design. Reuse Techniques for VLSI Design is an invaluable reference for researchers and engineers involved in VLSI/ASIC design. |
Sadržaj
ECSI VSIA AND MEDEA HOW INTERNATIONAL ORGANISATIONS SUPPORT REUSABILITY | 1 |
12 The Systemonachip Challenge | 2 |
14 VSIA The Virtual Socket Interface Alliance | 4 |
15 MEDEA The Eureka Project on MicroElectronic Development for European Applications | 6 |
ANALYZING THE COST OF DESIGN FOR REUSE | 9 |
22 Introduction | 10 |
24 Specific and Reusable Blocks | 13 |
25 Comparing Reusable and Specific Components | 16 |
67 IP Repository | 75 |
68 Next Steps | 77 |
A REUSE LIBRARY APPROACH IN ENGINEERING CONTEXT | 79 |
72 Project Description and Objectives | 80 |
73 Reuse Methodology | 81 |
74 Module Administration | 84 |
75 Presentation and Access to Modules | 86 |
76 Measurement | 88 |
26 Conclusion | 19 |
A FLEXIBLE CLASSIFICATION MODEL FOR REUSE OF VIRTUAL COMPONENTS | 21 |
32 Objective | 22 |
34 RMS Similarity Metric | 24 |
35 The RMSTaxonomy | 27 |
36 Extended RMSClassification | 29 |
37 Implemenation | 31 |
38 Application of the Model | 32 |
39 Conclusion and Outlook | 35 |
AN INTEGRATED APPROACH TOWARDS A CORPORATE DESIGN REUSE STRATEGY | 37 |
42 Why is Design Reuse Difficult? | 39 |
43 Core Supply Process | 40 |
44 Organization | 43 |
45 Business Models | 44 |
46 Ensuring Core Quality | 45 |
48 The Overall Strategy | 47 |
DESIGN METHODOLOGY FOR IP PROVIDERS | 49 |
52 IP Database Structure | 50 |
53 Documentation of IP | 51 |
54 Simulation Testbench Philosophy | 53 |
55 Release Management | 56 |
57 Scalable DesignObjects | 58 |
58 Experience from Reuse Projects | 59 |
59 Conclusions | 61 |
HARD IP REUSE METHODOLOGY FOR EMBEDDED CORES | 63 |
62 Simulation Model Generation | 64 |
63 StaterKit Simulation Environment | 65 |
64 Timing Characterization and Timing Models | 67 |
65 Frontend View and Embedded Core Test Methodologies | 71 |
66 Backend Views and Backend Design | 73 |
78 Conclusion | 89 |
ASPECTS OF REUSE IN THE DESIGN OF MIXEDSIGNAL SYSTEMS | 91 |
82 Introduction | 92 |
84 Databases and Reuse | 94 |
85 Summary | 101 |
DESIGN REUSE EXPERIMENT FOR ANALOG MODULES DREAM | 103 |
92 Requirements for Reuse of Analog Blocks | 104 |
93 Implementation | 105 |
94 Experience | 107 |
95 Future Work | 108 |
96 Acknowledgement | 109 |
REDESIGN OF AN MPEG2HDTV VIDEO DECODER CONSIDERING REUSE ASPECTS | 111 |
102 Design Reuse | 112 |
103 Redesign of an MPEG2HDTV Video Decoder | 116 |
104 Design by Reuse Inverse Quantiser | 118 |
105 Design for Reuse IDCT Inverse Discrete Cosine Transform | 119 |
106 Summary | 122 |
REUSE CONCEPTS IN GROPIUS | 125 |
112 Introduction | 126 |
113 Gropius a Survey | 127 |
115 Everything can be Abbreaviated | 131 |
117 Parameterization with Circuits | 132 |
1110 Uniform Communication Protocol at the System Level | 135 |
1111 Conclusion | 136 |
LEGAL ASPECTS OF REUSE OF INTELLECTUAL PROPERTY | 139 |
122 Legal Situation | 140 |
123 Contractual and Technical Remedies | 142 |
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Uobičajeni izrazi i fraze
Adder algorithmic application architecture attributes automation basic behaviour business model cells chip circuit descriptions clock complex Computer concept core definition Core Supply Process coversheet defined described design flow design for reuse design methodology design reuse DesignObjects dfg-terms documentation ECSI effort environment Ergip example Figure functionality GDSII Gropius hard IP hardware description language IDCT implementation input integration Intellectual Property internal IP block IP provider Karlsruhe keywords library element logic MEDEA module netlist node operational amplifiers output parameters Place and Route reusable component reuse library reuser Robert Bosch GmbH scripts Semiconductor Shaper Siemens Semiconductor similarity metric simulation specific standard static timing analysis structure synthesis system level systems-on-a-chip Table taxonomy testbench tion University of Karlsruhe verification Verilog VHDL video decoder virtual components VSIA
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