Virtual Components Design and ReuseRalf Seepold, Natividad Martinez Madrid Springer Science & Business Media, 2001 - Broj stranica: 229 Design reuse is not just a topic of research but a real industrial necessity in the microelectronic domain and thus driving the competitiveness of relevant areas like for example telecommunication or automotive. Most companies have already dedicated a department or a central unit that transfer design reuse into reality. All main EDA conferences include a track to the topic, and even specific conferences have been established in this area, both in the USA and in Europe. Virtual Components Design and Reuse presents a selection of articles giving a mature and consolidated perspective to design reuse from different points of view. The authors stem from all relevant areas: research and academia, IP providers, EDA vendors and industry. Some classical topics in design reuse, like specification and generation of components, IP retrieval and cataloguing or interface customisation, are revisited and discussed in depth. Moreover, new hot topics are presented, among them IP quality, platform-based reuse, software IP, IP security, business models for design reuse, and major initiatives like the MEDEA EDA Roadmap. |
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Ostala izdanja - Prikaži sve
Virtual Components Design and Reuse Ralf Seepold,Natividad Martinez Madrid Pregled nije dostupan - 2010 |
Virtual Components Design and Reuse Ralf Seepold,Natividad Martinez Madrid Pregled nije dostupan - 2014 |
Uobičajeni izrazi i fraze
2-blocks Abstract State Machine access procedures addr algorithm analysis application application software approach architecture ASIC assigned attributes behavior block ciphers case-based reasoning checkers circuit clock co-design communication communication protocol complex configuration constraints CORBA ctrl database defined design automation design flow design methodology design reuse DOWNTO embedded systems entity environment example Figure formal verification frame component functional functional analysis hardware Hardware Description Language HardWWWired hierarchical identified implementation input interface specification IP core IP reuse Java language levels of abstraction mapping module node objects output parameters performance ports preprocessor problem Proc protocol query Q reset reusable RT components silicon simulation solution SPARC standard std_logic structure synthesis system design system level Table testbench tion transaction Verilog VHDL code VHDL descriptions VHDL Design VHDL+ virtual components workflow write_en
Popularni odlomci
Stranica 218 - C. Rust, J . Stroop and J. Tacken, "The Design of Embedded Real-Time Systems using the SEA Environment", in Proc. of the 5th Annual Australasian Conference on Parallel And Real-Time Systems (PART '98), Adelaide. Australia, 1998.
Stranica 209 - G. Boriello. A New Interface Specification Methodology and its Application to Transducer Synthesis.
Reference za ovu knjigu
System Specification & Design Languages: Best of FDL'02 Eugenio Villar,Jean Mermet,Jean P. Mermet Pregled nije dostupan - 2003 |